1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a system configuration of a semiconductor memory device having an array of dynamic memory cell units each of which is a NAND type structure or has a plurality of MOS transistors connected in series and a plurality of information storage capacitors each connected at its one end to the source of a respective one of the MOS transistors.
2. Description of the Related Art
As a type of dynamic random access memory (DRAM) a system has been developed recently in which a plurality of memory cells are connected in series to form a memory cell unit (a NAND type of memory cell unit), and such memory cell units are arrayed. It is an advantage of this cell array scheme is that there are few bit-line-to-cell contacts and hence the area of each cell can be decreased.
With this type of DRAM, for reading and rewriting of data, data stored in memory cells of each memory cell unit is read out in time sequence and then held temporarily in predetermined registers. The read data must be rewritten into the DRAM in time sequence. Thus, it takes long time to read and rewrite data. In addition, another read operation is not allowed during this data reading and rewriting operation. Thus much time is wasted.
As described above, problems with the conventional semiconductor memory device having an array of NAND type DRAM memory cell units are that a data reading and rewriting operation needs a long time, and no access to other data is allowed during that data reading and rewriting operation.